Paper Title
IMPLEMENTATION OF FAULT TOLERANT MEMORY BASED UART THROUGH SPI INTERFACEAbstract
In nanometer technologies, circuits are more and more sensitive to various kinds of perturbations. Alpha particles and atmospheric neutrons induce single-event upsets, affecting memory cells, latches, and flip-flops. They also induce single-event transients, initiated in the combinational logic and captured by the latches and flip-flops associated with the outputs of this logic. In the past, the major efforts were related on memories. However, as the whole situation is getting worse, solutions that protect the entire design are mandatory. Solutions for detecting the error in logic functions already exist, but there are only few solutions allowing the correction, leading to a lot of hardware overhead in non processor design. In this paper, we present a novel technique that includes UART architectures and an SPI for their implementations, which reduces the cost of dealys in any kinds of circuit.
KEYWORDS : UART,SPI